Talks

2022

  1. Intel Invited
    Hardware Compilation with MLIR and CIRCT
    In Intel Strategic CAD Labs (SCL) Tech Presentation, 2022
  2. DAC’22 Poster
    PolyAIE: A Dataflow Compiler for Heterogeneous Compute Platforms
    In Design Automation Conference (DAC), 2022
  3. HPCA’22
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In International Symposium on High-Performance Computer Architecture (HPCA), 2022
  4. FPGA’22 Invited
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In FPGA Workshop on Open-Source Source-to-Source Transformation for High-Level Synthesis (HLS), 2022

2021

  1. Gatech Invited
    Compilers for Domain-Specific Accelerators
    In Gatech ECE6100/CS6290 (Advanced Computer Architecture) Guest Lecture, 2021
  2. UIUC Invited
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In UIUC CS Compiler Seminar, 2021
  3. A3D3 Invited
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In Accelerated AI Algorithms for Data-Driven Discovery (A3D3) Kick-off Meeting, 2021
  4. UIUC Invited
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In UIUC ECE527 (System-on-Chip Design) Guest Lecture, 2021
  5. CIRCT
    FSM (Finite-State Machine) Dialect in CIRCT
    In Circuit IR Compilers and Tools (CIRCT) Open Meeting, 2021
  6. Xilinx Invited
    ScaleHLS: Scalable High-Level Synthesis through MLIR
    In Xilinx Adaptive Compute Clusters (XACC) Tech Talk Series, 2021
  7. CCF Invited
    CIRCT: The Next-Generation Open-Source Hardware Compilation Framework based on MLIR (in Chinese)
    In CCF Agile Hardware Development and Open-Source EDA Forum, 2021
  8. UCSC Invited
    ScaleHLS: Scalable High-Level Synthesis through MLIR
    In UCSC Hardware Systems Collective (HSC) Seminar, 2021
  9. LATTE’21
    ScaleHLS: Scalable High-Level Synthesis through MLIR
    In ASPLOS Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), 2021

2020

  1. UIUC
    HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
    In UIUC Ph.D. Qualifying Exam, 2020
  2. OSDT Invited
    Handshake-based High-Level Synthesis in CIRCT (in Chinese)
    In Open-Source Development Tools (OSDT) Open Meeting, 2020
  3. CIRCT
    Handshake-based High-Level Synthesis in CIRCT
    In Circuit IR Compilers and Tools (CIRCT) Open Meeting, 2020
  4. DAC’20
    HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
    In Design Automation Conference (DAC), 2020

2018

  1. ICSICT’18
    A Resource-Sharing and Pipelined Design Scheme for Dynamic Deployment of CNNs on FPGAs
    In International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018