Talks

2024

  1. Intel Invited
    HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
    In Intel HLD (High-level Design) Reading Group, 2024
    Slides

2023

  1. HACC Invited
    HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
    In AMD-UIUC Center of Excellence Seminars, 2023
    Slides Website
  2. UIUC
    Scalable High-Level Synthesis for AI Accelerator Design and Verification
    In UIUC Ph.D. Preliminary Exam, 2023
    Slides
  3. UIUC Guest Lecture
    MLIR, ScaleHLS, and HIDA
    In UIUC ECE527 (System-On-Chip Design) Guest Lecture, 2023
    Slides Website
  4. TECHCON’23
    ScaleFlow: High-Level Synthesis for Large Dataflow Applications
    In The Semiconductor Research Corporation (SRC) TECHCON, 2023
    Slides Website
  5. Google Invited
    ScaleFlow: Scalable High-Level Synthesis for Dataflow Applications
    In Google X Journal Club, 2023
    Slides

2022

  1. UIUC Guest Lecture
    MLIR and ScaleHLS
    In UIUC ECE527 (System-On-Chip Design) Guest Lecture, 2022
    Slides Website
  2. Intel Invited
    Hardware Compilation with MLIR and CIRCT
    In Intel Strategic CAD Labs (SCL) Tech Presentation, 2022
    Slides
  3. HPCA’22
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In International Symposium on High-Performance Computer Architecture (HPCA), 2022
    Slides Website
  4. FPGA’22 Invited
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In FPGA Workshop on Open-Source Source-to-Source Transformation for High-Level Synthesis (HLS), 2022
    Slides Website

2021

  1. Gatech Guest Lecture
    Compilers for Domain-Specific Accelerators
    In Gatech ECE6100/CS6290 (Advanced Computer Architecture) Guest Lecture, 2021
    Slides Website
  2. UIUC Invited
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In UIUC CS Compiler Seminar, 2021
    Slides
  3. UIUC Guest Lecture
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    In UIUC ECE527 (System-On-Chip Design) Guest Lecture, 2021
    Slides Website
  4. CIRCT Invited
    FSM (Finite-State Machine) Dialect in CIRCT
    In Circuit IR Compilers and Tools (CIRCT) Open Meeting, 2021
    Slides Website
  5. Xilinx Invited
    ScaleHLS: Scalable High-Level Synthesis through MLIR
    In Xilinx Adaptive Compute Clusters (XACC) Tech Talk Series, 2021
    Slides Video Website
  6. CCF Invited
    CIRCT: The Next-Generation Open-Source Hardware Compilation Framework based on MLIR (in Chinese)
    In CCF Agile Hardware Development and Open-Source EDA Forum, 2021
    Slides Website
  7. UCSC Invited
    ScaleHLS: Scalable High-Level Synthesis through MLIR
    In UCSC Hardware Systems Collective (HSC) Seminar, 2021
    Slides Video Website
  8. LATTE’21
    ScaleHLS: Scalable High-Level Synthesis through MLIR
    In ASPLOS Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), 2021
    Slides Video Website

2020

  1. UIUC
    HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
    In UIUC Ph.D. Qualifying Exam, 2020
    Slides
  2. OSDT Invited
    Handshake-based High-Level Synthesis in CIRCT (in Chinese)
    In Open-Source Development Tools (OSDT) Open Meeting, 2020
    Slides Video Website
  3. CIRCT Invited
    Handshake-based High-Level Synthesis in CIRCT
    In Circuit IR Compilers and Tools (CIRCT) Open Meeting, 2020
    Slides Website
  4. DAC’20
    HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
    In Design Automation Conference (DAC), 2020
    Slides Video Website

2018

  1. ICSICT’18
    A Resource-Sharing and Pipelined Design Scheme for Dynamic Deployment of CNNs on FPGAs
    In International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018
    Slides Website