Welcome! My name is Hanchen Ye (叶汉辰) and I’m an Electrical and Computer Engineering PhD candidate in University of Illinois at Urbana-Champaign (UIUC) advised by professor Deming Chen. Before joining UIUC, I obtained my Bachelor and Master degree in Fudan University (复旦大学) in 2017 and 2019, respectively.
My research lies in the area of High-level Synthesis (HLS), Compilers, FPGA, and Hardware Acceleration. Recently, I’m focused on HLS optimization (ScaleHLS), emerging hardware compilation tools (CIRCT), and high-efficiency computing of DNN applications (HybridDNN and DNNExplorer). I’m most skilled in C++, Verilog, and Python.
Check my resumé.
During this summer in Xilinx, I participated in an open-source project, CIRCT (Circuit IR Compilers and Tools), which is an effort looking to apply MLIR and the LLVM development methodology to the domain of hardware design tools. I contributed to a dynamic scheduling based High-Level Synthesis (HLS) flow, and a StaticLogic dialect for representing statically scheduled circuits during the process of HLS. Now, we are excited to see that the CIRCT project officially becomes an incubator project of LLVM!
Our new paper “DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator” was accepted by ICCAD'20. This paper proposes a novel DNN accelerator design paradigm which can take advantage of both pipeline and generic structure, and proposes an efficient design space exploration (DSE) engine to generate the optimized DNN accelerator following the new paradigm. All accepted papers of ICCAD'20 are shown in this page.