Hanchen Ye

Hanchen Ye

PhD Student in UIUC

About Me

Welcome! My name is Hanchen Ye (叶汉辰) and I’m an Electrical and Computer Engineering PhD candidate in University of Illinois at Urbana-Champaign (UIUC) advised by professor Deming Chen. Before joining UIUC, I obtained my Bachelor and Master degree in Fudan University (复旦大学) in 2017 and 2019, respectively.

My research lies in the area of High-level Synthesis (HLS), Compilers, FPGA, and Hardware Acceleration. Recently, I’m focused on HLS optimization (ScaleHLS), emerging hardware compilation tools (CIRCT), and high-efficiency computing of DNN applications (HybridDNN and DNNExplorer). I’m most skilled in C++, Verilog, and Python.

Check my resumé.

Work Experience

 
 
 
 
 
Compilers Intern
SiFive
May 2021 – Aug 2021 California
  • Affiliation: Platform Engineering Department
  • Advisor: Andrew Lenharth
 
 
 
 
 
Compiler Research Intern
Xilinx
Jun 2020 – Aug 2020 California
  • Affiliation: Xilinx Research Labs
  • Advisor: Stephen Neuendorffer
 
 
 
 
 
Research Assistant
University of Illinois at Urbana-Champaign
Aug 2019 – Present Illinois
  • Affiliation: CAD for Emerging Systems (ES-CAD) Group
  • Advisor: Deming Chen
 
 
 
 
 
Research Assistant
Fudan University
Sep 2016 – Jun 2019 Shanghai
  • Affiliation: State Key Laboratory of ASIC and System
  • Advisor: Gengsheng Chen

Education

 
 
 
 
 
PhD in Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Aug 2019 – Present Illinois
 
 
 
 
 
MEng in Integrated Circuit Engineering
Fudan University
Sep 2017 – Jun 2019 Shanghai
 
 
 
 
 
BE in Electrical and Computer Engineering (Exchange)
National University of Singapore
Aug 2015 – Dec 2015 Singapore
 
 
 
 
 
BE in Microelectronics Science and Engineering
Fudan University
Sep 2013 – Jun 2017 Shanghai

Posts

News: ScaleHLS Short Paper Presented on LATTE'21

Our short paper “ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR” was presented on LATTE'21 hold as an ASPLOS'21 workshop. This paper proposes an next-generation High-level Synthesis compilation flow based on MLIR.

News: CIRCT Open-Source Project Becomes a Part of LLVM

During this summer in Xilinx, I participated in an open-source project, CIRCT (Circuit IR Compilers and Tools), which is an effort looking to apply MLIR and the LLVM development methodology to the domain of hardware design tools. I contributed to a dynamic scheduling based High-Level Synthesis (HLS) flow, and a StaticLogic dialect for representing statically scheduled circuits during the process of HLS. Now, we are excited to see that the CIRCT project officially becomes an incubator project of LLVM!

News: DNNExplorer Paper Accepted by ICCAD'20

Our new paper “DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator” was accepted by ICCAD'20. This paper proposes a novel DNN accelerator design paradigm which can take advantage of both pipeline and generic structure, and proposes an efficient design space exploration (DSE) engine to generate the optimized DNN accelerator following the new paradigm. All accepted papers of ICCAD'20 are shown in this page.