ScaleHLS is a High-level Synthesis (HLS) compilation framework built on top of MLIR. ScaleHLS has been open-sourced on GitHub: https://github.com/hanchenye/scalehls. The preprint paper of ScaleHLS is also available on arXiv: https://arxiv.org/abs/2107.11673.

Our short paper “ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR” was presented on LATTE'21 hold as an ASPLOS'21 workshop. This paper proposes an next-generation High-level Synthesis compilation flow based on MLIR.

During this summer in Xilinx, I participated in an open-source project, CIRCT (Circuit IR Compilers and Tools), which is an effort looking to apply MLIR and the LLVM development methodology to the domain of hardware design tools. I contributed to a dynamic scheduling based High-Level Synthesis (HLS) flow, and a StaticLogic dialect for representing statically scheduled circuits during the process of HLS. Now, we are excited to see that the CIRCT project officially becomes an incubator project of LLVM!

Our new paper “DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator” was accepted by ICCAD'20. This paper proposes a novel DNN accelerator design paradigm which can take advantage of both pipeline and generic structure, and proposes an efficient design space exploration (DSE) engine to generate the optimized DNN accelerator following the new paradigm. All accepted papers of ICCAD'20 are shown in this page.