Publications

* denotes equal contribution

Papers

2024

  1. DATE’24
    ISDC: Feedback-guided Iterative SDC Scheduling for High-level Synthesis
    Hanchen Ye, David Pan, Chris Leary, Deming Chen, and Xiaoqing Xu
    In The Conference on Design, Automation & Test in Europe (DATE), 2024
    Code
  2. ASPLOS’24
    HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
    Hanchen Ye, Hyegang Jun, and Deming Chen
    In The ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2024
    PDF arXiv DOI Code
  3. ASP-DAC’24 Invited
    Software/Hardware Co-design for LLM and Its Application for Design Verification
    Jiaxin Wan*, Yingbing Huang*, Yuhong Li, Hanchen Ye, Jinghua Wang, Xiaofan Zhang, and Deming Chen
    In The Asia and South Pacific Design Automation Conference (ASP-DAC), 2024

2023

  1. TECHCON’23 Best Presenter
    ScaleFlow: High-Level Synthesis for Large Dataflow Applications
    Hanchen Ye, and Deming Chen
    In The Semiconductor Research Corporation (SRC) TECHCON, 2023
    PDF Code Website
  2. ISPD’23 Invited
    High-level Synthesis for Domain Specific Computing
    Hanchen Ye, Hyegang Jun, Jin Yang, and Deming Chen
    In The International Symposium on Physical Design (ISPD), 2023
    PDF DOI
  3. FPGA’23
    CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture
    Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Deming Chen, Jason Cong, and Peipei Zhou
    In The 31st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2023
    PDF arXiv DOI Code

2022

  1. TRETS Journal
    AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis
    HyeGang Jun, Hanchen Ye, Hyunmin Jeong, and Deming Chen
    The ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2022
    PDF DOI
  2. DAC’22 Invited
    ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations
    Hanchen Ye, HyeGang Jun, Hyunmin Jeong, Stephen Neuendorffer, and Deming Chen
    In The 59th ACM/IEEE Design Automation Conference (DAC), 2022
    PDF DOI Code
  3. HPCA’22
    ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, and Deming Chen
    In The 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022
    PDF arXiv DOI Code

2021

  1. MLBench’21
    Being-ahead: Benchmarking and Exploring Accelerators for Hardware-Efficient AI Deployment
    Xiaofan Zhang, Hanchen Ye, and Deming Chen
    In The Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench) of the Conference on Machine Learning and Systems (MLSys), 2021
    PDF arXiv Website
  2. LATTE’21
    ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR
    Hanchen Ye, Cong Hao, Hyunmin Jeong, Jack Huang, and Deming Chen
    In The Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE) of the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2021
    PDF Code Website

2020

  1. ICSICT’20
    IDLA: An Instruction-based Adaptive CNN Accelerator
    Peng Gao, Zhize Huang, Hanchen Ye, and Gengsheng Chen
    In The 15th IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020
    PDF DOI
  2. ICCAD’20
    DNNExplorer: a framework for modeling and exploring a novel paradigm of FPGA-based DNN accelerator
    Xiaofan Zhang*, Hanchen Ye*, Junsong Wang, Yonghua Lin, Jinjun Xiong, Wen-mei Hwu, and Deming Chen
    In The 39th ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2020
    PDF arXiv DOI
  3. DAC’20
    HybridDNN: A framework for high-performance hybrid DNN accelerator design and implementation
    Hanchen Ye, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, and Deming Chen
    In The 57th ACM/IEEE Design Automation Conference (DAC), 2020
    PDF arXiv DOI

2018

  1. ICSICT’18
    A Resource-Sharing & Pipelined Design Scheme for Dynamic Deployment of CNNs on FPGAs
    Hanchen Ye, and Gengsheng Chen
    In The 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018
    PDF DOI


Posters

2023

  1. DAC’23 1st Place Winner
    ScaleHLS: A Scalable High-Level Synthesis Framework
    In Ph.D. Forum of the ACM/IEEE Design Automation Conference (DAC), 2023
    Poster Website

2022

  1. ICCAD’22
    vHLS: Verifiable and Efficient High-Level Synthesis
    In Student Research Contest (SRC) of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2022
    Poster Website
  2. A3D3
    ScaleFlow: Scalable High-Level Synthesis for Large Dataflow Applications
    In Accelerated AI Algorithms for Data-Driven Discovery (A3D3) Annual Meeting, 2022
    Poster Website
  3. DAC’22
    PolyAIE: A Dataflow Compiler for Heterogeneous Compute Platforms
    In Young Fellow Program of the ACM/IEEE Design Automation Conference (DAC), 2022
    Poster Website