Papers
2024
[NeurIPS'24] SnapKV: LLM Knows What You are Looking for Before Generation
Yuhong Li*, Yingbing Huang*, Bowen Yang, Bharat Venkitesh, Acyr Locatelli, Hanchen Ye, Tianle Cai, Patrick Lewis, Deming Chen
The Conference on Neural Information Processing Systems (NeurIPS'24)
PDF / arXiv / GitHub
[TRETS] CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture (Journal)
Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Shixin Ji, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Yiyu Shi, Deming Chen, Jason Cong, Peipei Zhou
The ACM Transactions on Reconfigurable Technology and Systems (TRETS)
PDF / GitHub / DOI
[LAD'24] An Iteratively-refined Dataset for High-Level Synthesis Functional Verification through LLM-Aided Bug Injection
Lily Jiaxin Wan, Hanchen Ye, Jinghua Wang, Manvi Jha, Deming Chen
The IEEE International Workshop on LLM-Aided Design (LAD'24)
PDF / GitHub / DOI
[DAC'24] New Solutions on LLM Acceleration, Optimization, and Application (Invited)
Yingbing Huang, Lily Jiaxin Wan, Hanchen Ye, Manvi Jha, Jinghua Wang, Yuhong Li, Xiaofan Zhang, Deming Chen
The ACM/IEEE Design Automation Conference (DAC'24)
PDF / arXiv / DOI
[DATE'24] Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS
Hanchen Ye, David Pan, Chris Leary, Deming Chen, Xiaoqing Xu
The Conference on Design, Automation & Test in Europe (DATE'24)
PDF / arXiv / GitHub / Poster / Slides / DOI
[ASPLOS'24] HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
Hanchen Ye, Hyegang Jun, Deming Chen
The ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'24)
PDF / arXiv / GitHub / Poster / Slides / Website / DOI
[ASP-DAC'24] Software/Hardware Co-design for LLM and Its Application for Design Verification (Invited)
Lily Jiaxin Wan*, Yingbing Huang*, Yuhong Li, Hanchen Ye, Jinghua Wang, Xiaofan Zhang, Deming Chen
The Asia and South Pacific Design Automation Conference (ASP-DAC'24)
PDF / DOI
2023
[TECHCON'23] ScaleFlow: High-Level Synthesis for Large Dataflow Applications (
Best Student Presenter Award)
Hanchen Ye, Deming Chen
The Semiconductor Research Corporation (SRC) TECHCON (TECHCON'23)
PDF / GitHub / Slides / Website
[ISPD'23] High-level Synthesis for Domain Specific Computing (Invited)
Hanchen Ye, Hyegang Jun, Jin Yang, Deming Chen
The International Symposium on Physical Design (ISPD'23)
PDF / DOI
[FPGA'23] CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture
Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'23)
PDF / arXiv / GitHub / DOI
2022
[TRETS] AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis (Journal)
Hyegang Jun, Hanchen Ye, Hyunmin Jeong, Deming Chen
The ACM Transactions on Reconfigurable Technology and Systems (TRETS)
PDF / DOI
[DAC'22] ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations (Invited)
Hanchen Ye, Hyegang Jun, Hyunmin Jeong, Stephen Neuendorffer, Deming Chen
The ACM/IEEE Design Automation Conference (DAC'22)
PDF / GitHub / DOI
[HPCA'22] ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen
The IEEE International Symposium on High-Performance Computer Architecture (HPCA'22)
PDF / arXiv / GitHub / Slides / Website / DOI
2021
[MLBench'21] Being-ahead: Benchmarking and Exploring Accelerators for Hardware-Efficient AI Deployment
Xiaofan Zhang, Hanchen Ye, Deming Chen
The MLSys Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench'21)
PDF / arXiv / Website
[LATTE'21] ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR
Hanchen Ye, Cong Hao, Hyunmin Jeong, Jack Huang, Deming Chen
The ASPLOS Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'21)
PDF / Slides / Video / Website / GitHub
2020
[ICSICT'20] IDLA: An Instruction-based Adaptive CNN Accelerator
Peng Gao, Zhize Huang, Hanchen Ye, Gengsheng Chen
The IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT'20)
PDF / DOI
[ICCAD'20] DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator
Xiaofan Zhang*, Hanchen Ye*, Junsong Wang, Yonghua Lin, Jinjun Xiong, Wen-mei Hwu, Deming Chen
The ACM/IEEE International Conference on Computer-Aided Design (ICCAD'20)
PDF / arXiv / DOI
[DAC'20] HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
Hanchen Ye, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, Deming Chen
The ACM/IEEE Design Automation Conference (DAC'20)
PDF / arXiv / Slides / Video / DOI
2018
[ICSICT'18] A Resource-Sharing & Pipelined Design Scheme for Dynamic Deployment of CNNs on FPGAs
Hanchen Ye, Gengsheng Chen
The IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT'18)
PDF / Slides / DOI