Talks and Tutorials

2024

[FPGA'24] ScaleHLS-HIDA: From PyTorch/C++ to Highly-optimized HLS Accelerators (Tutorial)
Hanchen Ye, Junhao Pan, Deming Chen
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'24)
Slides / Website

[Intel] HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis (Invited)
Intel High-level Design (HLD) Reading Group (Intel)
Slides

2023

[HACC] HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis (Invited)
AMD-UIUC Center of Excellence Seminars (HACC)
Slides / Website

[UIUC] Scalable High-Level Synthesis for AI Accelerator Design and Verification
UIUC Ph.D. Preliminary Exam (UIUC)
Slides

[UIUC] MLIR, ScaleHLS, and HIDA (Guest Lecture)
UIUC ECE527 (System-On-Chip Design) Guest Lecture (UIUC)
Slides / Website

[Google] ScaleFlow: Scalable High-Level Synthesis for Dataflow Applications (Invited)
Google X Journal Club (Google)
Slides

2022

[UIUC] MLIR and ScaleHLS (Guest Lecture)
UIUC ECE527 (System-On-Chip Design) Guest Lecture (UIUC)
Slides / Website

[Intel] Hardware Compilation with MLIR and CIRCT (Invited)
Intel Strategic CAD Labs (SCL) Tech Presentation (Intel)
Slides

[FPGA'22] ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation (Invited)
The FPGA Workshop on Open-Source Source-to-Source Transformation for High-Level Synthesis (FPGA'22)
Slides / Website

2021

[Gatech] Compilers for Domain-Specific Accelerators (Guest Lecture)
Gatech ECE6100/CS6290 (Advanced Computer Architecture) Guest Lecture (Gatech)
Slides / Website

[UIUC] ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation (Invited)
UIUC CS Compiler Seminar (UIUC)
Slides

[UIUC] ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation (Guest Lecture)
UIUC ECE527 (System-On-Chip Design) Guest Lecture (UIUC)
Slides / Website

[CIRCT] FSM (Finite-State Machine) Dialect in CIRCT (Invited)
Circuit IR Compilers and Tools Open Meeting (CIRCT)
Slides / Website

[XACC] ScaleHLS: Scalable High-Level Synthesis through MLIR (Invited)
Xilinx Adaptive Compute Clusters Tech Talk Series (XACC)
Slides / Video / Website

[CCF] CIRCT: The Next-Generation Open-Source Hardware Compilation Framework based on MLIR (in Chinese) (Invited)
CCF Agile Hardware Development and Open-Source EDA Forum (CCF)
Slides / Website

[UCSC] ScaleHLS: Scalable High-Level Synthesis through MLIR (Invited)
UCSC Hardware Systems Collective (HSC) Seminar (UCSC)
Slides / Video / Website

2020

[UIUC] HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
UIUC Ph.D. Qualifying Exam (UIUC)
Slides

[OSDT] Handshake-based High-Level Synthesis in CIRCT (in Chinese) (Invited)
Open-Source Development Tools Open Meeting (OSDT)
Slides / Video / Website

[CIRCT] Handshake-based High-Level Synthesis in CIRCT (Invited)
Circuit IR Compilers and Tools Open Meeting (CIRCT)
Slides / Website