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'synthesizer' Submodule

Introduction

from streamtensor import synthesizer

Synthesizer module for generating Vitis HLS C++ code and running Vitis HLS tools.

This module provides a high-level interface to the StreamTensor synthesizer. It exposes a single class Synthesizer that takes a serialized MLIR module and a set of options, and runs Vitis HLS C simulation, synthesis, co-simulation, and linking targeting FPGA devices.

SynthesisConfig(synth_tool_path='v++', sim_tool_path='vitis-run', platforminfo_tool_path='platforminfo', part='xcu55c-fsvh2892-2L-e', platform_repo_path='/opt/xilinx/platforms', platform='xilinx_u55c_gen3x16_xdma_3_202210_1', xrt_path='/opt/xilinx/xrt', vitis_hls_path='/tools/Xilinx/Vitis_HLS/2023.2', clock_freqhz=150000000, optimize='0', start_fifo_depth=16, enable_tracing=False, tracing_kernels=None, tracing_hbm_port=31)

Synthesis configuration for Vitis HLS C synthesis.

Attributes:

Name Type Description
synth_tool_path str

Path to the Vitis HLS synthesis tool.
sim_tool_path str

Path to the Vitis HLS simulation tool.
platforminfo_tool_path str

Path to the Vitis HLS platforminfo tool.
part str

AMD FPGA part number.
platform_repo_path str

Path to the AMD platform repository.
platform str

AMD platform name.
xrt_path str

Path to the Xilinx runtime library.
vitis_hls_path str

Path to the Vitis HLS installation directory.
clock_freqhz int

Clock frequency in Hz.
optimize str

Optimization level, 0, 1, 2, 3, s, or quick.
start_fifo_depth int

FIFO depth for dataflow start signal.
enable_tracing bool

Enable device tracing during runtime.
tracing_kernels Optional[List[str]]

List of kernel names for tracing.
tracing_hbm_port int

HBM port number for tracing.

Parameters:

Name Type Description Default
synth_tool_path str

Path to the Vitis HLS synthesis tool.

 'v++'
sim_tool_path str

Path to the Vitis HLS simulation tool.

 'vitis-run'
platforminfo_tool_path str

Path to the Vitis HLS platforminfo tool.

 'platforminfo'
part str

AMD FPGA part number.

 'xcu55c-fsvh2892-2L-e'
platform_repo_path str

Path to the AMD platform repository.

 '/opt/xilinx/platforms'
platform str

AMD platform name.

 'xilinx_u55c_gen3x16_xdma_3_202210_1'
xrt_path str

Path to the Xilinx runtime library.

 '/opt/xilinx/xrt'
vitis_hls_path str

Path to the Vitis HLS installation directory.

 '/tools/Xilinx/Vitis_HLS/2023.2'
clock_freqhz int

Clock frequency in Hz.

 150000000
optimize str

Optimization level, 0, 1, 2, 3, s, or quick.

 '0'
start_fifo_depth int

FIFO depth for dataflow start signal.

 16
enable_tracing bool

Enable device tracing during runtime.

 False
tracing_kernels Optional[List[str]]

List of kernel names for tracing.

 None
tracing_hbm_port int

HBM port number for tracing.

 31

Synthesizer(work_path='.', config=SynthesisConfig())

Synthesizer class for generating Vitis HLS C++ code and running Vitis HLS tools.

Attributes:

Name Type Description
platform_path Path

Path to the platform file.
xrt_path Path

Path to the Xilinx runtime library.
vitis_hls_path Path

Path to the Vitis HLS installation directory.
work_path Path

Path to the working directory.
board_path Path

Path to the board directory.
binary_path Path

Path to the binary directory.
config SynthesisConfig

Synthesis configuration.

Parameters:

Name Type Description Default
work_path str

Path to the working directory.

 '.'
config SynthesisConfig

Synthesis configuration.

 SynthesisConfig()

generate_compile_config(kernel_name, root_path, design_paths, tb_paths, xo_path)

Generate compile configuration file for Vitis HLS C synthesis.

Parameters:

Name Type Description Default
kernel_name str

Name of the kernel function.

 required
root_path Path

Path to the configuration working directory.

 required
design_paths List[Path]

List of paths to the HLS C++ design files.

 required
tb_paths List[Path]

List of paths to the testbench files.

 required
xo_path Path

Path to the generated XO file.

 required

Returns:

Type Description
Path

Path to the generated compile configuration file.

generate_testbench(host_name, root_path, inputs=None, outputs=None)

Generate testbench files for Vitis HLS C simulation and co-simulation.

Parameters:

Name Type Description Default
host_name str

Name of the host function.

 required
root_path Path

Path to the testbench working directory.

 required
inputs Optional[Tuple[Tensor, ...]]

Tuple of input tensors.

 None
outputs Optional[Tuple[Tensor, ...]]

Tuple of output tensors.

 None

Returns:

Type Description
List[Path]

List of paths to the generated testbench files.

Raises:

Type Description
ValueError

If the tensor type is not supported.

run_host_generation(module, host_name, inputs, outputs)

Run Vitis runtime host application compilation.

Parameters:

Name Type Description Default
module Module

MLIR module.

 required
host_name str

Name of the host function.

 required
inputs Tensor | Tuple[Tensor, ...]

Tuple of input tensors.

 required
outputs Tensor | Tuple[Tensor, ...]

Tuple of output tensors.

 required

run_synthesis(module, host_name, kernel_name, inputs=None, outputs=None, csim=False, csynth=False, cosim=False, link=False)

Run Vitis HLS C simulation, synthesis, co-simulation, and linking.

Parameters:

Name Type Description Default
module Module

MLIR module.

 required
host_name str

Name of the host function.

 required
kernel_name str

Name of the kernel function or connectivity.

 required
inputs Optional[Tensor | Tuple[Tensor, ...]]

Tuple of input tensors.

 None
outputs Optional[Tensor | Tuple[Tensor, ...]]

Tuple of output tensors.

 None
csim bool

Run Vitis HLS C simulation.

 False
csynth bool

Run Vitis HLS C synthesis.

 False
cosim bool

Run Vitis HLS C/RTL co-simulation.

 False
link bool

Link Vitis HLS C/RTL.

 False

Returns:

Type Description
Path

Path to the compile directory.

Raises:

Type Description
AssertionError

If the kernel function or connectivity is not found.

generate_host(module, inputs, outputs, work_path='.', config=SynthesisConfig())

Generate all host applications in the MLIR module.

Parameters:

Name Type Description Default
module Module

MLIR module.

 required
inputs Tensor | Tuple[Tensor, ...]

Tuple of input tensors.

 required
outputs Tensor | Tuple[Tensor, ...]

Tuple of output tensors.

 required
work_path str

Path to the working directory.

 '.'
config SynthesisConfig

Synthesis configuration.

 SynthesisConfig()

get_type_name(tensor)

Get the C++ type name of a PyTorch tensor.

Parameters:

Name Type Description Default
tensor Tensor

PyTorch tensor.

 required

Returns:

Type Description
Optional[str]

C++ type name of the tensor.

replace_string_with_sed(file_path, old_string, new_string)

Replace a string in a file using the sed command.

Parameters:

Name Type Description Default
file_path str

Path to the file.

 required
old_string str

Old string to replace.

 required
new_string str

New string to replace with.

 required

simulate_kernel(module, host_name, kernel_name, inputs, outputs, work_path='.', cosim=True, config=SynthesisConfig())

Simulate a kernel in the MLIR module.

Parameters:

Name Type Description Default
module Module

MLIR module.

 required
host_name str

Name of the host function.

 required
kernel_name str

Name of the kernel function.

 required
inputs Tensor | Tuple[Tensor, ...]

Tuple of input tensors.

 required
outputs Tensor | Tuple[Tensor, ...]

Tuple of output tensors.

 required
work_path str

Path to the working directory.

 '.'
cosim bool

Run Vitis HLS C/RTL co-simulation.

 True
config SynthesisConfig

Synthesis configuration.

 SynthesisConfig()

synthesize_all_kernels(module, work_path='.', link=False, config=SynthesisConfig())

Synthesize all kernels in the MLIR module.

Parameters:

Name Type Description Default
module Module

MLIR module.

 required
work_path str

Path to the working directory.

 '.'
link bool

Link Vitis HLS C/RTL.

 False
config SynthesisConfig

Synthesis configuration.

 SynthesisConfig()