'hls' Dialect
An HLS out-of-tree MLIR dialect
This dialect contains dedicated operations, types, and attributes designed for representing HLS-specific structures and components in MLIR.
Operations¶
hls.connectivity (streamtensor::hls::ConnectivityOp)¶
Represent the connectivities between HLS modules
Syntax:
operation ::= `hls.connectivity` $sym_name $body attr-dict
Traits: HasParent<ModuleOp>, IsolatedFromAbove, NoTerminator
Interfaces: Symbol
Attributes:¶
| Attribute | MLIR Type | Description |
|---|---|---|
sym_name | ::mlir::StringAttr | string attribute |
hls.number_kernel (streamtensor::hls::NumberKernelOp)¶
Represent the number of compute units to be instantiated
Syntax:
operation ::= `hls.number_kernel` $kernelName `(` $numKernels `)` attr-dict `:` type($computeUnits)
Traits: HasParent<ConnectivityOp>
Interfaces: SymbolUserOpInterface
Attributes:¶
| Attribute | MLIR Type | Description |
|---|---|---|
kernelName | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
numKernels | ::mlir::IntegerAttr | 64-bit signed integer attribute |
Results:¶
| Result | Description |
|---|---|
computeUnits |
variadic of A compute unit type |
hls.stream_connection (streamtensor::hls::StreamConnectionOp)¶
Represent the stream connection between compute units
Syntax:
operation ::= `hls.stream_connection` $source `[` $sourcePort `]` `->` $target `[` $targetPort `]` `depth`
$fifoDepth attr-dict `:` type($source) `->` type($target)
Traits: HasParent<ConnectivityOp>
Attributes:¶
| Attribute | MLIR Type | Description |
|---|---|---|
sourcePort | ::mlir::StringAttr | string attribute |
targetPort | ::mlir::StringAttr | string attribute |
fifoDepth | ::mlir::IntegerAttr | 64-bit signed integer attribute |
Operands:¶
| Operand | Description |
|---|---|
source |
A compute unit type |
target |
A compute unit type |
hls.super_logic_region (streamtensor::hls::SuperLogicRegionOp)¶
Represent the super logic region of a compute unit
Syntax:
operation ::= `hls.super_logic_region` $computeUnit `SLR` `[` $index `]` attr-dict `:` type($computeUnit)
Traits: HasParent<ConnectivityOp>
Attributes:¶
| Attribute | MLIR Type | Description |
|---|---|---|
index | ::mlir::IntegerAttr | 64-bit signed integer attribute |
Operands:¶
| Operand | Description |
|---|---|
computeUnit |
A compute unit type |
hls.system_port (streamtensor::hls::SystemPortOp)¶
Represent the system port connection of a compute unit
Syntax:
operation ::= `hls.system_port` $computeUnit `[` $computeUnitPort `]` $tag `[` $indexMin `:` $indexMax `]`
attr-dict `:` type($computeUnit)
Traits: HasParent<ConnectivityOp>
Attributes:¶
| Attribute | MLIR Type | Description |
|---|---|---|
computeUnitPort | ::mlir::StringAttr | string attribute |
tag | ::mlir::StringAttr | string attribute |
indexMin | ::mlir::IntegerAttr | 64-bit signed integer attribute |
indexMax | ::mlir::IntegerAttr | 64-bit signed integer attribute |
Operands:¶
| Operand | Description |
|---|---|
computeUnit |
A compute unit type |
Attributes¶
MemoryKindAttr¶
Kind of memory
Syntax:
#hls.memory<
mlir::streamtensor::hls::MemoryKind # value
>
Parameters:¶
| Parameter | C++ type | Description |
|---|---|---|
| value | mlir::streamtensor::hls::MemoryKind |
an enum of type MemoryKind |
Types¶
ComputeUnitType¶
A compute unit type
Syntax:
!hls.cu<
::llvm::StringRef # name
>
Parameters:¶
| Parameter | C++ type | Description |
|---|---|---|
| name | ::llvm::StringRef |
Enums¶
MemoryKind¶
Kind of memory
Cases:¶
| Symbol | Value | String |
|---|---|---|
| UNKNOWN | 0 |
unknown |
| LUTRAM_2P | 1 |
lutram_2p |
| BRAM_2P | 2 |
bram_2p |
| URAM_2P | 3 |
uram_2p |
| BRAM_T2P | 4 |
bram_t2p |
| URAM_T2P | 5 |
uram_t2p |
| SRL_FIFO | 6 |
srl_fifo |
| LUTRAM_FIFO | 7 |
lutram_fifo |
| BRAM_FIFO | 8 |
bram_fifo |
| URAM_FIFO | 9 |
uram_fifo |
| DRAM | 10 |
dram |