Our new paper “ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation” was accepted by HPCA'22. In this paper, we propose a new tool, named as ScaleHLS, to tackle the challenges present in the representation, optimization, and exploration of HLS designs. ScaleHLS represents HLS designs with a multi-level IR for the first time, solves HLS optimization problems at the right levels of abstraction, and automates such optimizations through a new end-to-end flow. ScaleHLS can optimize large HLS designs and still deliver high QoR for FPGA hardware implementation.
ScaleHLS is a High-level Synthesis (HLS) compilation framework built on top of MLIR. ScaleHLS has been open-sourced on GitHub: https://github.com/hanchenye/scalehls. The preprint paper of ScaleHLS is also available on arXiv: https://arxiv.org/abs/2107.11673.
Our short paper “ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR” was presented on LATTE'21 hold as an ASPLOS'21 workshop. This paper proposes an next-generation High-level Synthesis compilation flow based on MLIR.
During this summer in Xilinx, I participated in an open-source project, CIRCT (Circuit IR Compilers and Tools), which is an effort looking to apply MLIR and the LLVM development methodology to the domain of hardware design tools. I contributed to a dynamic scheduling based High-Level Synthesis (HLS) flow, and a StaticLogic dialect for representing statically scheduled circuits during the process of HLS. Now, we are excited to see that the CIRCT project officially becomes an incubator project of LLVM!
Our new paper “DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator” was accepted by ICCAD'20. This paper proposes a novel DNN accelerator design paradigm which can take advantage of both pipeline and generic structure, and proposes an efficient design space exploration (DSE) engine to generate the optimized DNN accelerator following the new paradigm. All accepted papers of ICCAD'20 are shown in this page.
Our new paper “HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation” was accepted by DAC'20. This paper proposes a novel hybrid Spatial / Winograd convolution architecture for the DNN acceleration on FPGA. All accepted papers of DAC'20 are shown in this page. Full paper download will be available before April.
Our paper “A Resource-Sharing & Pipelined Design Scheme for Dynamic Deployment of CNNs on FPGAs” was presented on ICSICT'18. This paper proposes a Dynamic Partial Reconfiguration (DPR) -based pipeline architecture, which can make large CNNs accelerators adapt to resource-limited FPGAs while maintaining a low overall latency.
Our team Musketeers and project “An FPGA IoT Sensor-Hub Based on RISC-V” just won the 1st place winner of the UNIGROUP (紫光) design track in the 2nd China College IC Competition (中国大学生集成电路创新创业大赛). In this project, we designed a multi-functional FPGA IoT sensor-hub with a RISC-V CPU and an RT-Thread real-time operating system.
Totally 9 different design tracks supported by ADI, ARM, IEEE, NI, Huawei, YMTC (长江存储), C-SKY (中天微), Vimicro (中星微), and UNIGROUP were opened, and more than 900 teams participated in this competition.